Patent Document 1 (Japanese Patent Application Publication No. 2004-56134) discloses a flash memory cell including a semiconductor substrate, a first tunneling oxide film formed in a predetermined region of the semiconductor substrate, a first floating gate formed at an upper portion of the first tunneling oxide film, a second tunneling oxide film formed along an upper portion of the semiconductor substrate and one sidewall of the first floating gate, a second floating gate formed in contact with the second tunneling oxide film and isolated from the first floating gate, a dielectric film formed on the first floating gate and the second floating gate, a control gate formed on the dielectric film, a first junction region formed in the semiconductor substrate under one side portion of the second tunneling oxide film, and a second junction region formed in the semiconductor substrate under one side portion of the first tunneling oxide film (FIG. 14 of Patent Document 1). The structure of said flash memory cell is a 2-bit cell structure (4-level states), in which the first floating gate and the second floating gate are separated by the second tunneling oxide film (high-temperature oxide film) to store electric charge in the respective floating gates.